FPGA Implementation of a Multilayer Maze Router

This paper describes the design and implementation of an FPGA-based multilayer maze routing accelerator. The accelerator is implemented as an array of small processing elements that corresponds to the horizontal structure of the routing grid. Mulitilayer routing is efficiently implemented by time-multiplexing multiple layers over the twodimensional grid. Prototype accelerators supporiting 8 X 8 X 4 grids have been implemented and tested in a low-end Xilinx FPGA, and larger accelerators are now under development. Preliminary performance data shows speedups of 50-75 over software for an 8 X 8 X 4 grid; higher speedups are expected for larger grids.